1. Field of the Invention
The present invention relates to an information processor equipping a plurality of register files and to a method for switching those register files. More particularly, the present invention relates to a technique for reducing an overhead associated with an operation for switching those register files.
2. Description of the Related Art
Conventionally, an information processor equipping a plurality of register files has been well known. In this information processor, typically, a first register bank is assigned to a main routine, and a second register bank is assigned to a sub routine. When the sub routine is called from the main routine, the first register bank is switched to the second register bank. Also, when the sub routine is returned to the main routine, the second register bank is switched to the first register bank.
When the bank switching operation mentioned above is performed, in order to maintain a continuity between a process in the main routine and anther process in the sub routine, it is required that a content of a second register file constituting the second register bank for the sub routine agrees with a content of a first register file constituting the first register bank for the main routine. To accomplish this requirement, the following technique as been conventionally employed.
In a first conventional technique for the bank switching operation, such a method is employed that when the sub routine is called from the main routine, a first register bank used until that time is switched to a second register bank, and also a content of a first register file is copied to a second register file. In this case, there are a case of copying the entire content of the first register file, and a case of copying only a necessary portion of the content of the first register file. It should be noted that when the sub routine is returned to the main routine, only a process result obtained in the sub routine is returned to a particular register of the first register file by executing a special instruction immediately before this return.
FIG. 1 shows a block diagram representing a configuration of an information processor employing this first conventional technique. This information processor is composed of an instruction register 50, an instruction decoder 51, a first register file 52, a second register file 53, a selector 54, a selector 55, a bank switching control circuit 56 and an operation unit 57.
The instruction register 50 transiently stores therein an instruction read out from a main memory by using an instruction fetching mechanism (not shown). A content of this instruction register 50 is sent to the instruction decoder 51. The instruction decoder 51 extracts a register designation section in an instruction stored in the instruction register 50, and then sends as a register address RA to the first register file 52 and the second register file 53. This register address RA includes a read address RDA and a write address WRA.
Also, the instruction decoder 51 decodes an operation code section in the instruction, and generates a bank switch signal BK, a register transfer signal RT and an operation signal OP. The bank switch signal BK includes a signal CALL and a signal RET. The signal CALL is generated when a call instruction is set in the instruction register 50, and the signal RET is generated when a return instruction is set in the instruction register 50. The register transfer signal RT is generated when a register transfer instruction is set in the instruction register 50. This register transfer instruction is used to transfer a content of the first register file 52 to the second register file 53. Moreover, the operation signal OP is generated when instructions except the call instruction, the return instruction and the register transfer instruction, for example, various instructions such as an arithmetic operation instruction, a logical operation instruction, a comparison instruction and a movement instruction are set in the instruction register 50.
The first register file 52 is composed of 32 registers, and is used when a main routine is executed. When the register address RA from the instruction decoder 51 is sent to the first register file 52, a data is read out from a register specified by the read address RDA, within the first register file 52. This read out data is sent to an input terminal A of the selector 54 and an input terminal A of the selector 55. Also a data from the operation unit 57 is written to a register specified by the write address WRA, within the first register file 52 when the main routine is being executed.
The second register file 53 is composed of 32 registers, and is used when a sub routine is executed. When the register address RA from the instruction decoder 51 is sent to the second register file 53, a data is read out from a register specified by the read address RDA, within the second register file 53. This read out data is sent to an input terminal B of the selector 55. Also the data from the operation unit 57 is written to a register specified by the write address WRA, within the second register file 53 when the sub routine is being executed.
The selector 54 selects the data from the first register file 52 entered to the input terminal A or the data from the operation unit 57 entered to the input terminal B in accordance with the register transfer signal RT sent to a select terminal S, and sends the selected data to the second register file 53. That is, the input terminal A of the selector 54 is selected when the register transfer signal RT sent from the instruction decoder 51 is applied to the select terminal S of the selector 54. Accordingly, the data from the first register file 52 is directly transferred to the second register file 53 through this selector 54 (the data is not transferred through the operation unit 57). On the other hand, the input terminal B is selected when the register transfer signal RT sent from the instruction decoder 51 is not applied to the select terminal S of the selector 54. Accordingly, the data from the operation unit 57 is transferred to the second register file 53 through this selector 54.
The selector 55 selects any one of the data from the first register file 52 and the data from the second register file 53 in response to a control signal from the bank switching control circuit 56, and sends the selected data to the operation unit 57. The bank switching control circuit 56 generates the control signal to select the input terminal B of the selector 55 if receiving the signal CALL from the instruction decoder 51 and to select the input terminal A of the selector 55 if receiving the signal RET. Thus, the data from the first register file 52 is sent to the operation unit 57 during the execution of the main routine, and the data from the second register file 53 is sent to the operation unit 57 during the execution of the sub routine.
The operation unit 57 processes the data from the selector 55, in accordance with the operation signal OP from the instruction decoder 51. This processed result is stored in the register specified by the write address WRA, within the first register file 52, during the execution of the main routine, and is stored in the register specified by the write address WRA, within the second register file 53, during the execution of the sub routine.
In this information processor according to the first conventional technique, the register transfer instruction is executed immediately before the execution of the call instruction in the main routine so that the content of the first register file is copied to the second register file. As a result, the continuity between the process of the main routine and the process of the sub routine is retained.
In a second conventional technique for the bank switching operation, such a method is employed that when the sub routine is called from the main routine, a parameter is not transferred directly from the first register file to the second register file, and is transferred through the main memory. That is, in the main routine, prior to the call of the sub routine, the parameter to be set in the second register file is stored in a predetermined area of the main memory. On the other hand, in the sub routine, prior to the execution of the instruction in the sub routine, the parameter stored in the predetermined area of the main memory is loaded to the second register file. In this second conventional technique, a common register that can be accessed from both the main routine and the sub routine may be used instead of the main memory.
An information processor according to this second conventional technique does not require the data transfer path from the first register file 52 through the selector 54 to the second register file 53 shown in FIG. 1. This results in the configuration simpler than that of the information processor according to the first conventional technique.
Moreover, a third conventional technique for the bank switching operation is a technique referred to as a so-called register window. In this third conventional technique, as shown in FIG. 2, a register file is divided into a main routine area, a sub routine area and a common area. In this case, physical addresses 0 to 47 are given to the register file.
In this configuration, logical addresses 0 to 31 for main routine are used when the register file is accessed from the main routine. In this case, the logical addresses 0 to 15 are correlated to the physical addresses 16 to 31 and the logical addresses 16 to 31 are correlated to the physical addresses 0 to 16. Similarly, logical addresses 0 to 31 for sub routine are used when the register file is accessed from the sub routine. In this case, the logical addresses 0 to 15 are correlated to the physical addresses 16 to 31 and the logical addresses 16 to 31 are correlated to the physical addresses 32 to 47. Those correlations are established when the respective programs of the main routine and the sub routine are complied.
In this information processor, in the main routine, a common area specified by the logical addresses 0 to 15 for main routine is used as an exchange area of a parameter, and a main routine area specified by the logical addresses 16 to 31 is used as a work area. On the other hand, in the sub routine, a common area specified by the logical addresses 0 to 15 for sub routine is used as an exchange area of a parameter, and a sub routine area specified by the logical addresses 16 to 31 is used as a work area. In this case, the common area of the main routine is physically equal to the common area of the sub routine. Thus, in the main routine, it is not necessary to transfer the parameter to the register file for the sub routine when the sub routine is called. As a result, an overhead associated with the switching of the register bank can be reduced.
As an information processor related to this third conventional technique, Japanese Laid Open Patent Application (JP-A-Heisei 7-64857) discloses xe2x80x9cdata storage apparatusxe2x80x9d. In this third conventional technique, a first register file having a window configuration comprises a register having a read port and a write port. Then, a data access is performed between the first register file and a second register file corresponding to one window. In this data processor, a selected portion of the first register file is re-written to the second register file, in accordance with a value of a window pointer. This rewriting operation is performed when the value of the window pointer is changed. An access from an operating device to the register is treated as an access to the second register file. A register constituting the second register file has a read port and a write port for a data access to the first register file, in addition to the read ports and the write ports in which the number thereof correspond to the number of the operating devices. In this way, the size of the circuit in the entire register files is reduced by equipping the second register file between the operating device and the first register file having the window configuration.
However, in the information processor according to the first conventional technique, the data is actually transferred from the first register file to the second register file. Thus, a long time is required to carry out the bank switching operation. Actually, it usually takes one clock to transfer one data between the registers. If the number of registers is 32, 32 clocks are required to transfer all the data.
In this first conventional technique, all the data or the necessary data must be transferred prior to the execution of the sub routine. Thus, as the number of registers to be transferred is larger, the overhead of the data transfer associated with the switching of the register bank is larger. Moreover, since a function executed in the sub routine is simple, the operation time is less than 32 clocks, in many cases. In such a case, since a wait time in the operation unit 57 becomes longer, usage efficiency does not improve. Especially, a drop in a process performance of the information processor caused by the overhead of the data transfer brings about a problem in a real time process.
The information processor according to the second conventional technique exchanges the data between the main routine and sub routine through the main memory or the common register. Thus, it takes a long time to carry out this exchanging process, which brings about a drop in an effective process performance. Especially, when the data stored in the first register file is written to the second register file through a main memory having a slow access speed, it takes a long time to carry out the bank switching operation. Also, the information processor according to the first and second conventional techniques, if it is the information processor that can process a plurality of routines in parallel, needs to exclusively process the data between the routines. Hence, the overhead is further larger to thereby drop the process performance.
Moreover, the information processor according to the third conventional technique can quickly carry out the bank switching operation since it is not necessary to actually transfer the data from the first register file to the second register file. However, this third conventional technique has such a problem that the register can not be effectively used since the common area is fixed in hardware. For example, if a certain software sufficiently functions by using a few parameters when the sub routine is called while another software requires many parameters, there may be a situation that a non-used register is induced or that the number of registers is short because the size of the common area is fixed.
Also, the necessary data must be stored in advance in the common area in order to execute the sub routine without the data transfer. This reason is as follows. That is, in the sub routine, the data can not be directly read out from the area in the main routine, and in the main routine, the data can not be directly written to the area in the sub routine. Thus, it must be programmed or compiled such that the data to be commonly used in the main routine and the sub routine is selected and stored in the common area. Hence, a load on the software becomes heavy to thereby make the generality insufficient.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide an information processor which can quickly switch register files without influence of the number of parameters to be exchanged, and a method for switching the register files.
To achieve the above-described object, an information processor, according to a first aspect of the present invention, is featured by such an information processor including a first register file, a second register file, a controller, a first path, a second path and a third path. The first register is used when a first instruction is executed and the second register file is used when a second instruction is executed. The controller activates the second register file and deactivates the first register file, when the second instruction is called from the first instruction. The first path transfers a data read from the first register file if the data used by the second instruction is not written in the second register file which is activated by the controller when the second instruction is executed. The second path transfers the data read from the second register file if the data used by the second instruction is written in the second register file which is activated by the controller when the second instruction is executed. Also, the third path transfers an execution result obtained by executing the second instruction based on the data transferred from one of the first path and the second path to write into the second register file.
In this information processor, when a second instruction is called from a first instruction, a state in which a first register file is used is switched to another state in which a second register file is used. Then, when the second instruction is executed, if a data used by the second instruction is not still written into the second register file, the data obtained from the first register file is used to execute the second instruction and then an execution result is written into the second register file. Thus, it is not necessary to previously transfer the data used by the second instruction from the first register file to the second register file. Hence, an overhead can be suppressed when the register files are switched. Also, differently from the common area of the fixed size in the conventional register window, this is equivalent to a case in which only a register for storing therein the data used in the second instruction is used as the common area. Therefore, there is neither the occurrence of a non-used register nor the occurrence of lack of registers.
Also, to similarly achieve the above-explained object, an information processor, according to a second aspect of the present invention, is featured by such an information processor including a plurality of register files, a controller, a first path, a second path and a third path. The plurality of register files is used when a plurality of instructions is executed, respectively. The controller, when an instruction is called from another instruction, activates one of the plurality of register files corresponding to the instruction and deactivates remaining ones of the plurality of register files corresponding to the other instruction. The first path transfers a data read from one of the remaining register files if the data used by the instruction is not written in the one register file activated by the controller when the instruction is executed. The second path transfers the data read from the one register file if the data used by the instruction is written in the one register file activated by the controller when the instruction is executed. Also, the third path transfers an execution result obtained by executing the instruction based on the data transferred from one of the first path and the second path to write into the activated one register file.
This information processor can switch three or more register files by using little overhead to thereby enable a fast data process.
Also, to similarly achieve the above explained object, a register file switching method, according to a third aspect of the present invention, is featured by such a register file switching method including steps (a) to (d).
This register file switching method is applied in an information processor having a first register file used when a first instruction is executed and a second register file used when a second instruction is executed.
In the step (a), the second register file is activated and the first register file is deactivated, when the second instruction is called from the first instruction. In the step (b), a data read from the first register file is transferred if the data used by the second instruction is not written in the second register file which is activated at the step (a) when the second instruction is executed. In the step (c), the data read from the second register file is transferred if the data used by the second instruction is written in the second register file which is activated at the step (a) when the second instruction is executed. Also, in the step (d), an execution result obtained by executing the second instruction based on the data obtained at the step (b) and the step (c) is transferred to write into the second register file.
Also, to similarly achieve the above explained object, a register file switching method, according to a fourth aspect of the present invention, is featured by such a register file switching method including steps (a) to (d).
This register file switching method is applied in an information processor having a plurality of register files that are used when a plurality of instructions is executed respectively.
In the step (a), when an instruction is called from another instruction, one of the plurality of register files corresponding to the instruction is activated and remaining ones of the plurality of register files corresponding to the other instruction is deactivated. In the step (b), a data read from one of the remaining register files is transferred if the data used by the instruction is not written in the one register file activated at the step (a) when the instruction is executed. In the step (c), the data read from the one register file is transferred if the data used by the instruction is written in the one register file activated at the step (a) when the instruction is executed. Also, in the step (d), an execution result obtained by executing the instruction based on the data obtained at one of the step (b) and the step (c) is transferred to write into the activated one register file.
Moreover, to similarly achieve the above-explained object, an information processor, according to a fifth aspect of the present invention, is featured by such an information processor including a first register file, a second register file, a controller and an executing section. The first register file is used when a first instruction is executed. The second register file is used when a second instruction is executed. The controller activates the second register file and deactivates the first register file, when the second instruction is called from the first instruction. Also, the executing section receives a data transferred from the first register file if the data used by the second instruction is not written in the second register file activated by the controller when the second instruction is executed, the data transferred from the second register file if the data used by the second instruction is written in the second register file activated by the controller when the second instruction is executed, executes the second instruction based on the received data, and writes an execution result obtained by executing the second instruction into the second register file.